Title :
A mixed-mode ESD protection circuit simulation-design methodology
Author :
Feng, Haigang ; Chen, Guang ; Zhan, Rouying ; Wu, Qiong ; Guan, Xiaokang ; Xie, Haolu ; Wang, Albert Z H ; Gafiteanu, Roman
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
fDate :
6/1/2003 12:00:00 AM
Abstract :
On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35-μm CMOS and BiCMOS processes, are presented.
Keywords :
BiCMOS integrated circuits; CMOS integrated circuits; circuit simulation; electrostatic discharge; integrated circuit design; mixed analogue-digital integrated circuits; overvoltage protection; 0.18 micron; 0.35 micron; BiCMOS; CMOS; IC technologies; VDSM; electrothermal equations; mixed-mode ESD protection circuit; multiple-level coupling; on-chip electrostatic discharge protection design; simulation-design methodology; CMOS process; Circuit simulation; Circuit synthesis; Coupling circuits; Design methodology; Electrostatic discharge; Electrothermal effects; Equations; Predictive models; Protection;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.811978
