Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue

Author

Blecker, Eric B. ; McDonald, Thomas M. ; Erdogan, O.E. ; Hurst, Paul J. ; Lewis, Stephen H.

Author_Institution

Univ. of California, Davis, CA, USA

Volume

38

Issue

6

fYear

2003

fDate

6/1/2003 12:00:00 AM

Firstpage

1059

Lastpage

1062

Abstract

An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit two-stage pipelined algorithmic analog-to-digital converter. To minimize power dissipation and noise, the queue consists of only one sample-and-hold amplifier. At a sampling rate of 20 Msamples/s, the peak signal-to-noise-and-distortion ratio is 45 dB, and the spurious-free dynamic range is 62 dB. The total power dissipation is 25.4 mW from 3.0 V. The active analog area is 0.11 mm².

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; integrated circuit noise; low-power electronics; pipeline processing; sample and hold circuits; 25.4 mW; 3.0 V; 8 bit; CMOS integrated circuits; adaptive digital-calibration algorithm; algorithmic analog-to-digital converter; analog queue-based architecture; digital background calibration; noise; peak signal-to-noise-and-distortion ratio; power dissipation; sample-and-hold amplifier; sampling rate; simplified queue; spurious-free dynamic range; two-stage pipelined converter; Analog-digital conversion; CMOS analog integrated circuits; CMOS technology; Calibration; Dynamic range; Power amplifiers; Power dissipation; Sampling methods; Signal processing; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.811990

Filename

1202010