Micropower low-voltage analog filter in a digital CMOS process

Author

Krishnapura, Nagendra ; Tsividis, Yannis

Author_Institution

Columbia Univ., New York, NY, USA

Volume

38

Issue

6

fYear

2003

fDate

6/1/2003 12:00:00 AM

Firstpage

1063

Lastpage

1067

Abstract

Techniques for implementing micropower analog filters using digital CMOS process technology are described. PMOS devices operating in accumulation are used for the integration capacitors, and the voltage swing across them is limited by employing current-mode operation using the log domain approach. The latter is implemented using enhanced lateral bipolar transistors. A second-order low-pass filter with a cutoff frequency of 22 kHz, fabricated in a 0.25-μm digital CMOS technology, consumes 4.1 μW from a 1.5-V supply and has an rms output noise of 0.25 nA. The filter´s signal-to-noise ratio at 1% total harmonic distortion (THD) is 56 dB and its maximum S/(N+THD) is 45 dB. The chip occupies 0.085 mm².

Keywords

Butterworth filters; CMOS analogue integrated circuits; continuous time filters; current-mode circuits; harmonic distortion; integrated circuit design; integrated circuit noise; low-pass filters; low-power electronics; 0.25 micron; 1.5 V; 22 kHz; 4.1 muW; PMOS devices; accumulation; continuous-time filter; current-mode operation; cutoff frequency; digital CMOS process; enhanced lateral bipolar transistors; integration capacitors; log domain approach; micropower low-voltage analog filter; rms output noise; second-order Butterworth filter; second-order low-pass filter; signal-to-noise ratio; total harmonic distortion; voltage swing; Bipolar transistors; CMOS process; CMOS technology; Capacitors; Cutoff frequency; Digital filters; Low pass filters; MOS devices; Signal to noise ratio; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.811986

Filename

1202011