Adder methodology and design using probabilistic multiple carry estimates

A novel approach for designing estimated carry adders for use in asynchronous circuits is presented. It demonstrates that by using statistical probability of a carry being in a particular state, a 32-bit adder can be constructed in which for the majority of additions there is an improvement in the speed performance of the adder. This methodology shows that each time an additional carry is introduced for carry prediction there is a 50% gain in speed performance over the previous 32-bit addition. This novel adder methodology significantly reduces the addition time, and through simulation and design it has been shown that the 32-bit ESTC adder using multiple carries can dramatically achieve speed and/or area advantages over existing adder circuits. For example using four carries for prediction, comparisons in terms of delay-area product show performance savings of more than 41% over the carry select adder with ripple adder elements, and more than 26% over both carry lookahead and carry select adders based on carry lookahead elements.