Efficient substructure sharing methods for optimising the inner-product operations in Rijndael advanced encryption standard

The Rijndael advanced encryption standard (AES) contains two paired important transformations, MixColumns (inverse MixColumns) and SubByte (inverse SubBytes), the most crucial operations in the AES encryption /decryption processes. They consist of XOR-based inner production operations in GF(2⁸). In the paper, two substructure sharing methods are proposed to reduce the area cost of implementing these transformations. The first method exploits pure bit-level sharing with two optimisation stages, while the second method combines both the byte-level and bit-level techniques to further improve the area /speed performance. Comparisons in both the architectural-level designs and the technology-dependent cell-based implementations are given. An AES processor with iterative architecture is implemented using both a 0.18 μm UMC cell library and a Xilinx FPGA device. Experimental results show that the whole AES processor based on our proposed method can reduce area cost significantly compared with Synopsys area-optimised synthesis results or other previous implementations.