Design of c.c.d. delay lines with floating-gate taps

Multitapped c.c.d. analogue delay lines have been produced with the floating-gate, reset-sensing technique. Although the efficacy of the approach has been demonstrated, no comprehensive design procedure exists to enable systematic device design. Because the c.c.d. and its associated tapping circuitry is an active structure, the operational parameter relationships are extremely complex and dependent on many physical effects. Some of these individual processes have been previously associated with a particular operating parameter, but, usually, for a nontapped device configuration. This paper summarises the basic performance limiting processes of floating-gate tapped c.c.d. delay lines, and presents a quantitative basis for designs and also for further analytical studies. In particular, 3-phase surface-channel devices are considered, although the analyses may be extended to other c.c.d. formations. The equations presented are related to a simple design example based upon a specification achievable in practical devices.