A comparison of microcomputer-based implementations of cascaded and parallel speed and current loops in DC motor drives

The cascaded loop configuration is the standard configuration for speed and current loops in DC motor drives of medium and large power. An alternative is the parallel loop scheme, which is used in some fast response servomotor drive applications. The parallel loop scheme features the independent operation of the two loops and the operation of only one loop at any given time. The latter characteristic is an advantage in microprocessor implementations because shorter computation and execution times are obtained, allowing processor time for other functions. Improvements in the dynamic response of the speed loop can also be obtained. The two configurations are compared in terms of dynamic response, algorithmic implementation, and execution times. The problems associated with the smooth transfer of control between speed and current loops in the parallel scheme are discussed, and an efficient solution is proposed. Experimental transient responses and execution times for both schemes are presented and compared