Title :
A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O3 gate stack
Author :
Wu, D. ; Lindgren, A.-C. ; Persson, S. ; Sjoblom, G. ; von Haartman, M. ; Seger, J. ; Hellström, P.E. ; Olsson, J. ; Blom, H.-O. ; Zhang, S.-L. ; Ostling, M. ; Vainonen-Ahlgren, E. ; Li, W.-M. ; Tois, E. ; Tuominen, M.
Author_Institution :
IMIT, Kungliga Tekniska Hogskolan, Kista, Sweden
fDate :
3/1/2003 12:00:00 AM
Abstract :
Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.
Keywords :
Ge-Si alloys; MOSFET; alumina; chemical vapour deposition; dielectric thin films; hafnium compounds; hole mobility; interface states; isolation technology; semiconductor materials; titanium compounds; ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack; LOCOS isolation; Si/sub 0.7/Ge/sub 0.3/; TiN-Al/sub 2/O/sub 3/-HfAlO/sub x/-Al/sub 2/O/sub 3/; atomic layer chemical vapor deposition; current drive; effective mobility; low interface state density; peak transconductance; proof-of-concept pMOSFETs; selective epitaxy; strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET; strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel; subthreshold slope; universal hole mobility curve; Atomic layer deposition; CMOS technology; Chemical vapor deposition; Dielectrics; Epitaxial growth; Fabrication; Germanium silicon alloys; MOSFET circuits; Silicon germanium; Tin;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2003.809524
