DocumentCode :
1214256
Title :
Optimum and heuristic synthesis of multiple word-length architectures
Author :
Constantinides, George A. ; Cheung, Peter Y K ; Luk, Wayne
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll., London, UK
Volume :
13
Issue :
1
fYear :
2005
Firstpage :
39
Lastpage :
57
Abstract :
This paper explores the problem of architectural synthesis (scheduling, allocation, and binding) for multiple word-length systems. It is demonstrated that the resource allocation and binding problem, and the interaction between scheduling, allocation, and binding, are complicated by the existence of multiple word-length operators. Both optimum and heuristic approaches to the combined problem are formulated. The optimum solution involves modeling as an integer linear program, while the heuristic solution considers intertwined scheduling, binding, and resource word-length selection. Techniques are introduced to perform scheduling with incomplete word-length information, to combine binding and word-length selection, and to refine word-length information based on critical path analysis. Results are presented for several benchmark and artificial examples, demonstrating significant resource savings of up to 46% are possible by considering these problems within the proposed unified framework.
Keywords :
critical path analysis; integer programming; linear programming; processor scheduling; resource allocation; architectural synthesis problem; benchmarked example; binding problem; critical path analysis; heuristic synthesis; integer linear program; intertwined scheduling; multiple wordlength; optimum solution; resource allocation; resource wordlength selection; Delay; Digital signal processing; Field programmable gate arrays; High level synthesis; Information analysis; Performance analysis; Resource management; Signal processing algorithms; Time invariant systems; Binding; bitwidth; digital signal processing; field-programmable gate array; high-level synthesis; scheduling; word-length;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2004.840398
Filename :
1386264
Link To Document :
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