Investigation into effects of device variability on CMOS layout motifs

Sub-circuit motifs are proposed as a methodology for simulating the performance of sub-45 nm circuits exhibiting atomistic device fluctuations. Motifs allow the reduction of the problem space and create a standard motif library as a step in the design hierarchy for logic circuits. Device variability information from 3D simulation results is used that is incorporated into families of BSIM4 models. It is demonstrated how a thorough understanding of circuit behaviour can be obtained and the impact on current drive is illustrated by examining the effect of additional parasitic resistances.