Title :
Regular pipelined multipliers
Author_Institution :
Comput. Lab., Oxford Univ., UK
Abstract :
Two regular processor arrays for multiplying unsigned numbers are described. The essence is a structure that allows designs with different degrees of pipelining to be synthesised. The impact of varying the degree of pipelining on performance is assessed.
Keywords :
digital arithmetic; multiplying circuits; multiprocessing systems; pipeline processing; carry-save algorithm; performance aspects; pipelined multipliers; regular processor arrays; shift-add algorithm; unsigned numbers multiplication;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19890940
