A 10 bit 20 MS/s 3 V supply CMOS A/D converter

Author

Ito, Masao ; Miki, Takahiro ; Hosotani, Shiro ; Kumamoto, Toshio ; Yamashita, Yukihiro ; Kijima, Masaki ; Okuda, Takashi ; Okada, Keisuke

Author_Institution

System LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

29

Issue

12

fYear

1994

fDate

12/1/1994 12:00:00 AM

Firstpage

1531

Lastpage

1536

Abstract

A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI´s. In this A/D converter, redundant binary encoders named “twin encoders” enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 μm CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation

Keywords

CMOS integrated circuits; VLSI; analogue-digital conversion; decoding; encoding; interference suppression; 0.8 micron; 10 bit; 135 mW; 3 V; CMOS A/D converter; Si; bias circuit; comparators; differential amplifiers; double-metal CMOS technology; double-polysilicon process; monolithic ADC; multilevel tree decoding structure; onchip ADC; redundant binary encoders; single power supply; subranging architecture; substrate noise suppression; system VLSIs; twin encoders; CMOS technology; Capacitance; Circuits; Decoding; Inverters; Laboratories; Low voltage; Matrix converters; Power supplies; Switches;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.340427

Filename

340427