A 320 MHz CMOS triple 8 bit DAC with on-chip PLL and hardware cursor

Author

Reynolds, David

Author_Institution

Analog Devices Inc., Wilmington, MA, USA

Volume

29

Issue

12

fYear

1994

fDate

12/1/1994 12:00:00 AM

Firstpage

1545

Lastpage

1551

Abstract

A 320 MHz triple 8 bit DAC with on-chip phase-locked loop (PLL), hardware cursor function, and an architecture that relies on time-interleaved logic blocks is presented. Overall device performance is optimized by operating different portions of the circuit at different frequencies and combining parallelism with time-interleaving to minimize the hardware cost. Clock multiplication by the on-chip PLL improved the maximum frequency of operation of the prototype circuits by 20 percent. The PLL operates from 20-500 MHz and has a peak-to-peak jitter of 60 ps at an operating frequency of 432 MHz. The 10 mm×10 mm chip was fabricated in a 0.8 μm CMOS process and dissipates 1.54 W from a single 5 V supply

Keywords

CMOS integrated circuits; digital phase locked loops; digital-analogue conversion; 0.8 micron; 1.54 W; 20 to 500 MHz; 320 MHz; 5 V; 8 bit; CMOS triple DAC; D/A convertor; clock multiplication; hardware cursor function; onchip PLL; phase-locked loop; time-interleaved logic blocks; CMOS logic circuits; CMOS process; Clocks; Cost function; Frequency; Hardware; Jitter; Logic devices; Phase locked loops; Prototypes;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.340429

Filename

340429