Title :
A 6 GHz 68 mW BiCMOS phase-locked loop
Author :
Razavi, Behzad ; Sung, Janmye James
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
fDate :
12/1/1994 12:00:00 AM
Abstract :
The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 μm, 20 GHz BiCMOS technology is described. The circuit incorporates a voltage-controlled oscillator that senses and combines the transitions in a ring oscillator to achieve a period equal to two ECL gate delays. A mixer topology is also used that exhibits full symmetry with respect to its inputs and operates with supply voltages as low as 1.5 V. Dissipating 60 mW from a 2 V supply, the circuit has a tracking range of 300 MHz, an rms jitter of 3.1 ps, and phase noise of -75 dBc/Hz at 1 kHz offset
Keywords :
BiCMOS integrated circuits; jitter; phase locked loops; phase noise; 1 micron; 1.5 to 2 V; 20 GHz; 6 GHz; 60 mW; BiCMOS PLL; ECL gate delays; VCO; fully monolithic PLL; mixer topology; phase-locked loop; ring oscillator; voltage-controlled oscillator; BiCMOS integrated circuits; Frequency; Low voltage; Phase locked loops; Pulse amplifiers; Pulse shaping methods; Ring oscillators; Silicon; Voltage control; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
