Title :
A 100 MHz A/D interface for PRML magnetic disk read channels
Author :
Uehara, Gregory T. ; Gray, Paul R.
Author_Institution :
Dept. of Electr. Eng., Hawaii Univ., Honolulu, HI, USA
fDate :
12/1/1994 12:00:00 AM
Abstract :
An analog-to-digital interface IC suitable for PRML read channels with a 100 MHz output rate has been designed and fabricated in a 1.2 μm CMOS technology. The prototype IC contains a low-pass filter, symbol-rate equalizer, analog-to-digital converter, and generates all required clocks from a single external reference clock. The filters are implemented using a switched-capacitor parallel filter architecture used to implement a 3:1 decimation filter and a 3-tap programmable equalizer
Keywords :
CMOS integrated circuits; analogue-digital conversion; equalisers; low-pass filters; magnetic disc storage; maximum likelihood detection; partial response channels; switched capacitor filters; 1.2 micron; 100 MHz; A/D interface; CMOS technology; PRML magnetic disk read channels; analog-to-digital converter; analog-to-digital interface IC; clocks; decimation filter; external reference clock; low-pass filter; programmable equalizer; switched-capacitor parallel filter; symbol-rate equalizer; Analog integrated circuits; Analog-digital conversion; CMOS analog integrated circuits; CMOS integrated circuits; CMOS technology; Clocks; Equalizers; Low pass filters; Magnetic separation; Prototypes;
Journal_Title :
Solid-State Circuits, IEEE Journal of
