Title :
Evaluation of SEGR threshold in power MOSFETs
Author :
Allenspach, M. ; Brews, J.R. ; Mouret, I. ; Schrimpf, R.D. ; Galloway, K.F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abstract :
Bias values, determined experimentally to result in single-event gate rupture (SEGR) in power metal oxide semiconductor field effect transistors (MOSFETs), are used in 2-D device simulations, incorporating the experimental geometry. The simulations indicate that very short time oxide field transients occur for ion strikes when V/sub DS//spl ne/OV. These transients can affect SEGR through hole trapping and redistribution in the oxide.<>
Keywords :
hole traps; ion beam effects; power MOSFET; semiconductor device models; transients; 2D device simulations; SEGR threshold; VDMOS power transistor; bias values; carrier multiplication; hole trapping; ion strikes; oxide field transients; power MOSFETs; prestrike inversion layer; single-event gate rupture; Computational modeling; Electric breakdown; FETs; Geometry; MOSFETs; Neck; Power generation; Power transistors; Testing; Voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on
