DocumentCode :
1215898
Title :
SEU hardening of field programmable gate arrays (FPGAs) for space applications and device characterization
Author :
Katz, R. ; Barto, R. ; McKerracher, P. ; Carkhuff, B. ; Koga, R.
Author_Institution :
NASA Goddard Space Flight Center, Greenbelt, MD, USA
Volume :
41
Issue :
6
fYear :
1994
Firstpage :
2179
Lastpage :
2186
Abstract :
Field Programmable Gate Arrays (FPGAs) are being used in space applications because of attractive attributes: good density, moderate speed, low cost, and quick turn-around time. However, these devices are susceptible to Single Event Upsets (SEUs). An approach using triple modular redundancy (TMR) and feedback was developed for flip-flop hardening in these devices. Test data showed excellent results for this circuit topology. Total dose and Single Event Effect (SEE) testing have been performed on recently released technologies. Failures are analyzed and test methodology is discussed.<>
Keywords :
circuit feedback; failure analysis; field programmable gate arrays; flip-flops; integrated circuit reliability; integrated circuit testing; logic testing; programmable logic arrays; radiation effects; radiation hardening (electronics); redundancy; FPGA; SEU hardening; device characterization; feedback; field programmable gate arrays; flip-flop hardening; single event effect testing; single event upsets; space applications; test methodology; total dose testing; triple modular redundancy; Circuit testing; Costs; Failure analysis; Field programmable gate arrays; Flip-flops; Instruments; Laboratories; Performance evaluation; Single event upset; Space technology;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/23.340560
Filename :
340560
Link To Document :
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