Title :
Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits
Author :
Velazco, R. ; Bessot, D. ; Duzellier, S. ; Ecoffet, R. ; Koga, R.
Author_Institution :
Lab. de Genie Inf., IMAG, Grenoble, France
Abstract :
Two new CMOS memory cells, called HIT cells, designed to be SEU-immune are presented. Compared to previously reported design hardened solutions, the HIT cells feature better electrical performances and consume less silicon area. SEU tests performed on a prototype chip prove the efficiency of the approach.<>
Keywords :
CMOS memory circuits; VLSI; integrated circuit design; integrated circuit testing; radiation hardening (electronics); CMOS memory cells; HIT cells; SEU-immune IC; SEU-tolerant VLSI circuits; single event upset; CMOS logic circuits; CMOS memory circuits; Energy consumption; Feedback; Latches; Logic devices; Prototypes; Random access memory; Silicon; Very large scale integration;
Journal_Title :
Nuclear Science, IEEE Transactions on
