DocumentCode :
1216464
Title :
Evaluation of a method for estimating low-dose-rate irradiation response of MOSFETs
Author :
Khosropour, P. ; Fleetwood, D.M. ; Galloway, K.F. ; Schrimp, R.D. ; Calvel, P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Volume :
41
Issue :
6
fYear :
1994
Firstpage :
2560
Lastpage :
2566
Abstract :
A simple method for estimating the threshold-voltage shift due to low-dose-rate ionizing irradiation was recently proposed for power MOSFETs. In this work, the physical considerations governing the applicability of the method are examined. In addition to the power MOSFETs discussed in the previous paper, the method is applied to integrated MOSFETs from two different technologies and critically evaluated. For this method to work, the oxide trapped charge due to low-dose-rate irradiation should be the same as that following irradiation at the dose rates specified in MIL-STD-883D Method 1019.4, and the interface-trap density following low-dose-rate irradiation should be the same as that following irradiation at 1019.4 rates and subsequent high-temperature annealing. Of the two integrated technologies evaluated, the method correctly predicts the low-dose-rate threshold-voltage shift for one, but not for the other. In the case where the method yields the correct result, the agreement appears to be coincidental. The results, coupled with the necessity for transistor-level test structures, suggests that the proposed method is applicable primarily to power MOSFETs that exhibit slow annealing of oxide-trapped charge and no rebound during low-dose-rate irradiation.<>
Keywords :
annealing; power MOSFET; radiation effects; semiconductor device reliability; semiconductor device testing; MIL-STD-883D Method 1019.4; dose rates; high-temperature annealing; integrated MOSFETs; integrated technologies; interface-trap density; low-dose-rate ionizing irradiation; low-dose-rate irradiation; low-dose-rate irradiation response; low-dose-rate threshold-voltage shift; oxide trapped charge; oxide-trapped charge; physical considerations; power MOSFETs; slow annealing; threshold-voltage shift; transistor-level test structures; Annealing; Contracts; Ionizing radiation; Laboratories; MOS devices; MOSFETs; Paper technology; Power engineering computing; Testing; Threshold voltage;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/23.340616
Filename :
340616
Link To Document :
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