Title :
A 14 ns 256 K×1 CMOS SRAM with multiple test modes
Author :
Voss, Peter H. ; Pfennings, Leo C M G ; Phelan, Cathal G. ; Connell, Cormac M O ; Davies, Thomas J. ; Ontrop, Hans ; Bell, Simon A. ; Salters, Roelof H W
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fDate :
8/1/1989 12:00:00 AM
Abstract :
A methodology to enter and exit from test modes in asynchronous static RAMs (SRAMs) is presented. This chip is fabricated in a 0.7 μm twin-tub, single-poly, double-metal technology on p/p+ epitaxial substrate. To prevent hot-electron degradation, a voltage regulator is used in the memory matrix, with the cascoding technique applied in the periphery. Circuits were implemented against voltage bumps and data glitching on the output. A small cell size of 5.1×13.7 μm2 and a chip size of 3.9×9.5 mm2 have been achieved
Keywords :
CMOS integrated circuits; VLSI; integrated memory circuits; random-access storage; 0.7 micron; 14 ns; 256 kbit; asynchronous static RAMs; cascoding technique; cell size; chip size; data glitching; double-metal technology; memory matrix; multiple test modes; p/p+ epitaxial substrate; test modes; twin-tub; voltage bumps; voltage regulator; Circuit testing; Degradation; Laboratories; Low earth orbit satellites; Matrix converters; Packaging; Random access memory; Switches; Timing; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
