Title :
A 32 kbyte integrated cache memory
Author :
Sawada, Kazuhiro ; Sakurai, Takayasu ; Nogami, Kazutaka ; Shirotori, Tsukasa ; Takayanagi, Toshinari ; Iizuka, Tetsuya ; Maeda, Takeo ; Matsunaga, Junichi ; Fuji, Hiromichi ; Maeguchi, Kenji ; Kobayashi, Kiyoshi ; Ando, Tomoyuki ; Hayakashi, Yoshiki ; Miy
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
8/1/1989 12:00:00 AM
Abstract :
The system, circuit, layout and device levels of an integrated cache memory (ICM), which includes 32 kbyte DATA memory with typical address to HIT delay of 18 ns and address to DATA delay of 23 ns, are described. The ICM offers the largest memory size and the fastest speed ever reported in a cache memory. The device integrates a 32 kbyte DATA INSTRUCTION memory, a 34 kbit TAG memory, an 8 kbit VALID flat, a 2 kbit least recently used (LRU) flag, comparators, and CPU interface logic circuits on a chip. The inclusion of the DATA memory is crucial in improving system cycle time. The device uses several novel circuit design technologies, including a double-word-line scheme, low-noise flush clear, a low-power comparator, noise immunity, and directly testable memory design. Its newly proposed way-slice architecture increases both flexibility and expandability
Keywords :
VLSI; buffer storage; integrated memory circuits; 18 ns; 23 ns; 32 KB; CPU interface logic circuits; DATA delay; DATA memory; HIT delay; TAG memory; comparators; directly testable memory design; double-word-line scheme; integrated cache memory; layout; least recently used; low-noise flush clear; low-power comparator; noise immunity; speed; system cycle time; way-slice architecture; Added delay; Cache memory; Central Processing Unit; Circuit noise; Circuit synthesis; Circuit testing; Logic circuits; Read-write memory; Semiconductor device noise; Technical Activities Guide -TAG;
Journal_Title :
Solid-State Circuits, IEEE Journal of
