DocumentCode :
1216895
Title :
New nibbled-page architecture for high-density DRAMs
Author :
Numata, Kenji ; Oowaki, Yukihito ; Itoh, Yasuo ; Hara, Takahiko ; Tsuchida, Kenji ; Ohta, Masako ; Watanabe, Shigeyoshi ; Ohuchi, Kazunori
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Volume :
24
Issue :
4
fYear :
1989
fDate :
8/1/1989 12:00:00 AM
Firstpage :
900
Lastpage :
904
Abstract :
A nibbled-page architecture which can be used to access all column addresses on the selected row address randomly in units of 8 bits at the 100 Mbit/s data rate is discussed. To realize such high-speed architecture, three key circuit techniques have been developed. An on-chip interleaved circuit has been used for the high-speed serial READ and WRITE operations. Column address prefetch and WE signal prefetch techniques have been introduced to eliminate idle time between 8 bit units. The nibbled-page architecture has been successfully implemented in an experimental 16 Mb DRAM, and 100 Mb/s operation has been achieved. The DRAM with nibbled-page mode is very effective in simplifying the design of high-speed data transfer systems
Keywords :
VLSI; integrated memory circuits; random-access storage; 100 Mbit/s; 16 Mbit; column addresses; high-density DRAMs; high-speed data transfer systems; idle time; nibbled-page architecture; on-chip interleaved circuit; prefetch; selected row address; Circuits; Content addressable storage; Prefetching; Random access memory; Timing; Ultra large scale integration;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.34068
Filename :
34068
Link To Document :
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