Title :
A 5.6 MIPS call-handling processor for switching systems
Author :
Hayashi, Takao ; Saita, Yasuaki ; Ohno, Toshiaki ; Morita, Takashi ; Fukuda, Takuma ; Yoshida, Shinji ; Ikeda, Renya
Author_Institution :
NEC Corp., Kawasaki, Japan
fDate :
8/1/1989 12:00:00 AM
Abstract :
A 32 bit call-handling processor for an electronic switching system (ESS) capable of a 5.6 MIPS instruction execution rate is discussed. The processor uses a mixed architecture consisting of a reduced instruction set computer (RISC) and a complex instruction set computer (CISC) to economize the instruction execution, and features a four-stage two-way pipeline and local storage for the RISC and writable control storage for the CISC. To obtain reliability, availability, and serviceability, such functions as parity check/generation, microdiagnostic, and matcher have been incorporated within the chip. The chip contains about 160 K transistors within a chip size of 13.2×13.7 mm2. A 1.2 μm double-metal CMOS technology has been used. In designing the chip layout, a compromise between manual and automatic placing or routing was adopted which enabled a reasonably short design time
Keywords :
CMOS integrated circuits; electronic switching systems; microprocessor chips; pipeline processing; reduced instruction set computing; 1.2 micron; 32 bits; 5.6 MIPS; CISC; ESS; RISC; automatic placing; call-handling processor; design time; double-metal CMOS technology; electronic switching system; four-stage two-way pipeline; local storage; matcher; microdiagnostic; parity check/generation; switching systems; writable control storage; Availability; CMOS technology; Computer aided instruction; Computer architecture; Electronic switching systems; Parity check codes; Pipelines; Reduced instruction set computing; Routing; Switching systems;
Journal_Title :
Solid-State Circuits, IEEE Journal of
