A data simulator for performance monitoring of vlsi ethernet hardware

The paper describes the design and operation of a microprocessor-based direct memory access data simulator for monitoring the performance of an Ethernet node. The node hardware is based on recently available special-purpose VLSI devices and has been designed to permit the transmission of packetised data and speech at a rate of 10 Mbits/s. An example of the benefit of using such a design tool in time-critical applications is given. It is concluded that such a simulator is an important development aid in the design of low-cost Ethernet hardware.