Electronic component model minimization based on log simulated annealing

A new systematic methodology is proposed in order to extract a simplified yet accurate equivalent schematic from S parameter measurements of electronic devices throughout a given frequency range. In this approach the two following successive processes are iteratively performed: a model parameter extraction and a model topology simplification. Thus the extraction problem must be solved automatically and iteratively without any foresight of magnitude orders for the model parameters. To prevent the process from being trapped into any local optimum, an optimization algorithm that combines the principles of simulated annealing and a specific logarithmic exploration has been developed. This algorithm, called “log simulated annealing” (LSA), allows handling of continuously valued variables within arbitrary large exploration domains. Furthermore, the method described in this paper requires a tight coupling between optimization and simulation. Therefore it was tested using a specifically developed linear circuit simulator