DocumentCode
1217521
Title
VLSI array synthesis for polynomial GCD computation and application to finite field division
Author
Jeong, Yong-Jin ; Burleson, Wayne
Author_Institution
Massachusetts Univ., Amherst, MA, USA
Volume
41
Issue
12
fYear
1994
fDate
12/1/1994 12:00:00 AM
Firstpage
891
Lastpage
897
Abstract
Many practical algorithms have dynamic (or data-dependent) dependency structure in their computation, which is not desirable for VLSI hardware implementation. Polynomial GCD computation by Euclid´s algorithm is a typical example of dynamic dependency. In this paper, we use an algorithmic transformation technique to derive static (or data-independent) dependencies for Euclid´s GCD algorithm. The resulting algorithm is mapped to a linear systolic array which is area-efficient and achieves maximum throughput with pipelining. It has m0+n 0+1 processing elements, where m0 and n0 are degrees of two polynomials. We have applied the technique to the extended GCD algorithm and developed a systolic finite field divider, which can be efficiently used in decoding a variety of error correcting codes
Keywords
VLSI; decoding; digital signal processing chips; error correction codes; pipeline arithmetic; signal flow graphs; systolic arrays; Euclid´s algorithm; VLSI array synthesis; algorithmic transformation technique; decoding; dynamic dependency; error correcting codes; finite field division; greatest common divisor; linear systolic array; maximum throughput; pipelining; polynomial GCD computation; processing elements; Computer applications; Decoding; Galois fields; Hardware; Heuristic algorithms; Pipeline processing; Polynomials; Systolic arrays; Throughput; Very large scale integration;
fLanguage
English
Journal_Title
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
Publisher
ieee
ISSN
1057-7122
Type
jour
DOI
10.1109/81.340851
Filename
340851
Link To Document