High throughput pipelined 2D Discrete cosine transform for video compression

This paper proposes an architecture and Verilog design of fast pipelined Two Dimensional Discrete Cosine Transform (2D DCT) on FPGA with quantization which can be used as a core in video compression hardware. In this design, the methodologies adopted are to use highly parallel and heavily pipelined circuits in order to increase the throughput and to be platform independent, whether an implementation uses a FPGA or an ASIC. The scheme incorporates dual-redundant input image memory, 45 stages of pipelining, and an optimized controller design yielding a throughput of one coefficient per clock cycle at 100 MHz. Speed improvement of 30 percent has been achieved and hardware resource are efficiently saved by reducing arithmetic operators. This design aimed to be implemented on Xilinx Spartan 3E XC3S1500E FPGA.