Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS

Author

Razavi, Behzad ; Lee, Kwing F. ; Yan, Ran H.

Author_Institution

AT&T Bell Labs., Holmdel, NJ, USA

Volume

30

Issue

2

fYear

1995

fDate

2/1/1995 12:00:00 AM

Firstpage

101

Lastpage

109

Abstract

Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 μm CMOS technology. Configured as a master-slave circuit, the divider achieves a maximum speed of 13.4 GHz with a power dissipation of 28 mW. The phase-locked loop employs a current-controlled oscillator and a symmetric mixer to operate at 3 GHz with a tracking range of ±320 MHz, an rms jitter of 2.5 ps, and a phase noise of -100 dBc/Hz while dissipating 25 mW

Keywords

CMOS digital integrated circuits; digital phase locked loops; frequency dividers; 0.1 micron; 1/2 frequency divider; 13.4 GHz; 25 mW; 28 mW; 3 GHz; PLL; current-controlled oscillator; deep submicron CMOS; high-speed operation; low-power frequency dividers; master-slave circuit; phase-locked loops; symmetric mixer; CMOS technology; Circuits; Frequency conversion; High speed optical techniques; Master-slave; Optical frequency conversion; Oscillators; Phase locked loops; Power dissipation; Tracking loops;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.341736

Filename

341736