Title :
Design of tapered buffers with local interconnect capacitance
Author :
Cherkauer, Brian S. ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
fDate :
2/1/1995 12:00:00 AM
Abstract :
This paper presents a design methodology and analytic relationships for the optimal tapering of cascaded buffers which consider the effects of local interconnect capacitance. The method, constant capacitance-to-current ratio tapering (C3RT), is based on maintaining the capacitive load to current drive ratio constant, and therefore, the propagation delay of each buffer stage also remains constant. Reductions in power dissipation of up to 22% and reductions in active area of up to 46%, coupled with reductions in propagation delay of up to 2%, as compared with tapered buffers which neglect local interconnect capacitance, are exhibited for an example buffer system
Keywords :
CMOS digital integrated circuits; buffer circuits; capacitance; cascade networks; integrated circuit design; integrated circuit interconnections; cascaded buffers; constant capacitance-to-current ratio tapering; design methodology; local interconnect capacitance; optimal tapering; power dissipation reduction; propagation delay; tapered buffers; Capacitance; Coupling circuits; Degradation; Design methodology; Driver circuits; Integrated circuit interconnections; Inverters; Power dissipation; Power system interconnection; Propagation delay;
Journal_Title :
Solid-State Circuits, IEEE Journal of
