An efficient multilevel placement technique using hierarchical partitioning

Author

Hamada, Takeo ; Cheng, Chung-Kuan ; Chau, Paul M.

Author_Institution

California Univ., La Jolla, CA, USA

Volume

39

Issue

6

fYear

1992

fDate

6/1/1992 12:00:00 AM

Firstpage

432

Lastpage

439

Abstract

Ratio cut hierarchical partitioning, which enables efficient multilevel simulated annealing, is applied to the row placement problem for large circuits. An overlapping moving window scheme is used to compensate for the effect of partitioning on the placement quality. Through the use of hierarchical partitioning, the asymptotic run time complexity of this algorithm grows linearly as the function of the circuit size. The system is called placement by ratio cut partitioning (PRC). The results from several benchmark tests are presented demonstrating PRC to be 2.49% on average better than TimberWolfSC Ver5.6. Furthermore, the run time for PRC is 18.3% on average less than that required for TimberWolfSC Ver5.6 for large test cases with more than 2000 cells. For a 100-K sea of gates test case, a 7.09% reduction in total wire length over TimberWolfSC Ver5.6 and a 51.7% saving in CPU time were achieved

Keywords

VLSI; circuit layout CAD; computational complexity; integrated circuit technology; simulated annealing; CAD; CPU time; IC layout; VLSI; asymptotic run time complexity; hierarchical partitioning; large circuits; multilevel placement technique; multilevel simulated annealing; overlapping moving window scheme; ratio cut partitioning; row placement problem; Central Processing Unit; Circuit simulation; Computational modeling; Lapping; Partial response channels; Partitioning algorithms; Processor scheduling; Simulated annealing; Testing; Wire;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.153634

Filename

153634