DocumentCode
1219619
Title
MOS multiplier/divider cell for analogue VLSI
Author
Khachab, N.I. ; Ismail, Mahamod
Author_Institution
Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA
Volume
25
Issue
23
fYear
1989
Firstpage
1550
Lastpage
1552
Abstract
A novel all-MOS continuous-time multiplier/divider parameterised cell is introduced. It comprises eight MOS transistors and a single operational amplifier. The new cell is highly reconfigurable, versatile, extremely simple to design and its output its conveniently programmed via DC control voltages. Some of the many applications of the new cell in analogue VLSI signal processing include analogue multiplication, signal squaring, division, signal inversion, amplitude modulation and RMS/DC conversion. Moreover, the new cell is easily extendable to achieve analogue vector multiplication, and hence it lends itself naturally to analogue MOS VLSI implementation of feedback/feedforward neural networks.
Keywords
MOS integrated circuits; VLSI; analogue circuits; dividing circuits; multiplying circuits; DC control voltages; MOS continuous-time multiplier/divider parameterised cell; RMS/DC conversion; amplitude modulation; analogue VLSI; analogue vector multiplication; feedback/feedforward neural networks; operational amplifier; signal inversion; signal processing; signal squaring;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19891042
Filename
138786
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