DocumentCode :
1219998
Title :
Modeling and characterization of the polymer stud grid array (PSGA) package: electrical, thermal and thermo-mechanical qualification
Author :
Chandrasekhar, Arun ; Vandevelde, Bart ; Driessens, Evelien ; Beyne, Eric ; De Raedt, Walter ; Pieters, Philip ; Nauwelaers, Bart ; Van Puymbroeck, Jef
Author_Institution :
IMEC, Leuven, Belgium
Volume :
26
Issue :
1
fYear :
2003
Firstpage :
54
Lastpage :
67
Abstract :
We characterize the polymer stud grid array (PSGA) package electrically, thermally and thermo-mechanically for successful commercial application. For the electrical characterization, we extract lumped parameter resistance-inductance-capacitance (RLC) models for the interconnects from simulations. We also measure the RF performance of the package on printed circuit board (PCB) test structures. The average self-inductance from the wirebond pad to the bottom of the stud is 0.53 nH and the total capacitance to the ground is 0.26 pF for an interconnection of the periphery of the over the edge (OTE) type PSGA. The lumped RLC model is verified by full three-dimensional (3-D) EM simulations. Simulation models also indicate that the "Micro-via" (μ-via) type of interconnection on the PSGA package improves performance by decreasing the inductance on an average by 60%. Thermal characterization involves the development of a steady-state thermal compact model with six nodes for the 72-pin PSGA. We also perform transient thermal measurements on test packages to fine-tune the detailed model. For the thermo-mechanical case we test the first level and second level reliability by experiments and optimize them using simulations. The board level reliability for the 72-pin PSGA mounted on a PCB is very high (N50%>10000 cycles). Simulations also show a higher reliability for the PSGA than the plastic ball grid array (PBGA).
Keywords :
equivalent circuits; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; modelling; thermal analysis; 0.26 pF; 3D EM simulations; Micro-via type; PCB test structures; PSGA package characterization; RF performance; board level reliability; electrical characterization; electrical qualification; first level reliability; interconnects; lumped parameter RLC models; over the edge type PSGA; package interconnection; package modeling; polymer stud grid array package; resistance-inductance-capacitance models; second level reliability; steady-state thermal compact model; thermal qualification; thermo-mechanical qualification; transient thermal measurements; Circuit simulation; Circuit testing; Electrical resistance measurement; Integrated circuit interconnections; Packaging; Polymers; Printed circuits; Qualifications; Radio frequency; Thermomechanical processes;
fLanguage :
English
Journal_Title :
Electronics Packaging Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-334X
Type :
jour
DOI :
10.1109/TEPM.2003.813009
Filename :
1205223
Link To Document :
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