DocumentCode
1220064
Title
Efficient nonblocking switching networks for interprocessor communications in multiprocessor systems
Author
Shao, Fong-Chih ; Oruç, A. Yavuz
Author_Institution
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
Volume
6
Issue
2
fYear
1995
fDate
2/1/1995 12:00:00 AM
Firstpage
132
Lastpage
141
Abstract
The performance of a multiprocessor system depends heavily on its ability to provide conflict free paths among its processors. In this paper, we explore the possibility of using a nonblocking network with O(N log N) edges (crosspoints) to interconnect the processors of an N processor system, We combine Bassalygo and Pinsker´s implicit design of strictly nonblocking networks with an explicit construction of expanders to obtain a strictly nonblocking network with -765.18N+352.8N log N edges and 2+log(N/5) depth. We present an efficient parallel algorithm for routing connection requests on this network and implement it on three parallel processor topologies. The implementation on a parallel processor whose processing elements are interconnected as in the Bassalygo-Pinsker network requires O(N log N) processing elements, O(N log N) interprocessor links and it takes O(log N) steps to route any single connection request where each step involves a small number (≈72) of bit-level operations. A contracted or folded version of the same implementation reduces the processing element count to O(N) without increasing the link count or the routing time. Finally, we establish that the same algorithm takes O(log3 N) steps on a perfect shuffle processor with O(N) processing elements. These results improve the crosspoint, depth and routing time complexities of the previously reported strictly nonblocking networks
Keywords
communication complexity; multiprocessor interconnection networks; parallel algorithms; performance evaluation; Bassalygo-Pinsker network; connection request routing; efficient nonblocking switching networks; efficient parallel algorithm; expanders; interprocessor communications; interprocessor links; multiprocessor systems; parallel processor topologies; routing time complexities; Bandwidth; Communication switching; Fasteners; Graph theory; Helium; Intelligent networks; Multiprocessing systems; Network topology; Parallel algorithms; Routing;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/71.342124
Filename
342124
Link To Document