Three-dimensional effects in dynamically triggered CMOS latchup

Author

Fiegna, Claudio ; Selmi, Luca ; Sangiorgi, Enrico ; Riccò, Bruno

Author_Institution

Dept. of Electron., Bologna Univ., Italy

Volume

36

Issue

9

fYear

1989

fDate

9/1/1989 12:00:00 AM

Firstpage

1683

Lastpage

1690

Abstract

An analysis of three-dimensional (3-D) effects in CMOS latchup under dynamic conditions that expands on previous work limited to steady state is presented. Measurements of the minimum duration of voltage pulses and the ramp slew rate needed to induce latchup and have been performed on devices of different widths and layouts, and the latchup susceptibility to transient stimuli has been found to depend on the device dimensions and geometry. By means of simple analytical models it is shown that such a dependence originates from the nonideal scaling of the distributed resistances and capacitances due to the 3-D nature of the structure terminating regions

Keywords

CMOS integrated circuits; integrated circuit technology; semiconductor device models; transients; 3D effects; analytical models; device dimensions; devices geometry; distributed capacitance; distributed resistances; dynamically triggered CMOS latchup; latchup susceptibility to transient stimuli; minimum duration of voltage pulses; nonideal scaling; parasitic p-n-p-n devices; parasitic thyristors; ramp slew rate; structure terminating regions; Geometry; Parasitic capacitance; Performance evaluation; Pulse measurements; Pulsed power supplies; Space vector pulse width modulation; Steady-state; Testing; Transient analysis; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.34230

Filename

34230