Abstract :
The IBM system z10 includes four microprocessor cores - each with a private 3-Mbyte cache - and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10´s CPU performance.
Keywords :
cryptography; data compression; mainframes; microprocessor chips; microwave devices; multiprocessor interconnection networks; IBM z10 processor; SMP hub chip; cryptography; data compression; decimal floating-point computation; frequency 4.4 GHz; high-frequency design technique; next-generation mainframe microprocessor; symmetric multiprocessor scaling interconnection; Acceleration; Computer architecture; Cryptography; Data compression; Fabrics; Hardware; High performance computing; Microprocessors; Reduced instruction set computing; Switches; Hot Chips 19; accelerators; branch prediction; decimal floating-point; high-frequency design; mainframe; microprocessor; pipeline; reliability; symmetric multiprocessor (SMP);
