Title :
RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology
Author :
Lam, Sang ; Wan, Hui ; Su, Pin ; Wyatt, Peter W. ; Chen, C.L. ; Niknejad, Ali M. ; Hu, Chenming ; Ko, Ping K. ; Chan, Mansun
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
4/1/2003 12:00:00 AM
Abstract :
The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET´s is investigated from the RF perspective. With the expected low gate resistance R/sub G/, the metal T-gate FD-SOI MOSFET achieves a higher f/sub max/ of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower f/sub T/ of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances C/sub gs/ and C/sub gd/ respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.
Keywords :
CMOS integrated circuits; MOSFET; capacitance; field effect MMIC; radiofrequency integrated circuits; silicon-on-insulator; 35 GHz; 67 GHz; RF characterization; RF performance; Si; fully-depleted SOI CMOS technology; gate resistance; metal T-gate structure; parasitic capacitances; self-aligned polysilicon gate; source-drain structure; CMOS integrated circuits; CMOS technology; Guidelines; High speed integrated circuits; Integrated circuit technology; MOSFET circuits; Parasitic capacitance; Radio frequency; Radiofrequency integrated circuits; Silicon on insulator technology;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2003.810892
