• DocumentCode
    1223367
  • Title

    B.C.D. multipliers

  • Author

    Webster, Max B. ; Baker, Paul W.

  • Author_Institution
    University of New South Wales, Department of Computer Science, School of Electrical Engineering, Sydney, Australia
  • Volume
    2
  • Issue
    5
  • fYear
    1979
  • fDate
    10/1/1979 12:00:00 AM
  • Firstpage
    226
  • Lastpage
    230
  • Abstract
    B.C.D. versions of known multiplier designs are presented; both achieve fast multiplication times without the high hardware cost typically associated with high speed. Serial b.c.d. addition and r.o.m. single-digit multipliers permit the substantial reductions in hardware cost, while higher clock frequencies offset the inherent slowness of the serial methods. Greatest cost-effectiveness is seen to be achieved through l.s.i. implementationn of a serial design which is easily extended for higher radix b.c.d. multiplication.
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Journal on
  • Publisher
    iet
  • ISSN
    0140-1335
  • Type

    jour

  • DOI
    10.1049/ij-cdt.1979.0049
  • Filename
    4809307
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1223367