25 ps resolution, 12-bit, 64 channel FASTBUS time-to-digital converter

Author

Sobczynski, C.W. ; Haynes, B.W. ; Skubic, M.J. ; Thielman, H.L.

Author_Institution

Kinetics Syst. Corp., Lockport, IL, USA

Volume

36

Issue

1

fYear

1989

fDate

2/1/1989 12:00:00 AM

Firstpage

426

Lastpage

430

Abstract

The design and performance of a 64-channel time-to-digital converter are presented. The full-scale time range of 100 ns is digitized to 12 bits, providing 25-ps resolution. Surface-mount components and digital correction techniques have been used to achieve both the high density and high performance of the device, which is housed in a single-width FASTBUS module. Efficient readout capabilities, including sparse data scans and block transfers of zero-suppressed channel data, are provided. The device also features common start operation linearity over the 100-ns full-scale time range on the order of ±50 ps, fast clear time (200 ns) and conversion time (300 μm); and onboard pedestal subtraction and hit register

Keywords

analogue-digital conversion; counting circuits; data acquisition; nuclear electronics; 12 bit; 25 ps; 64-channel time-to-digital converter; block transfers; common start operation linearity; conversion time; digital correction techniques; hit register; onboard pedestal subtraction; readout capabilities; resolution; single-width FASTBUS module; zero-suppressed channel data; CAMAC; Circuits; Differential amplifiers; Electronic equipment testing; Error correction; Fastbus; PROM; Physics; Registers; Voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.34477

Filename

34477