25 ps resolution, 12-bit, 64 channel FASTBUS time-to-digital converter

The design and performance of a 64-channel time-to-digital converter are presented. The full-scale time range of 100 ns is digitized to 12 bits, providing 25-ps resolution. Surface-mount components and digital correction techniques have been used to achieve both the high density and high performance of the device, which is housed in a single-width FASTBUS module. Efficient readout capabilities, including sparse data scans and block transfers of zero-suppressed channel data, are provided. The device also features common start operation linearity over the 100-ns full-scale time range on the order of ±50 ps, fast clear time (200 ns) and conversion time (300 μm); and onboard pedestal subtraction and hit register