Performance projections of scaled CMOS devices and circuits with strained Si-on-SiGe channels

Device and circuit simulations using a process/physics-based compact MOSFET model (UFPDB) are done to project the scaled CMOS speed-performance enhancement that can be expected from strained-Si channels on relaxed Si_1-xGe_x buffer layers in bulk Si. With the UFPDB process-based parameters associated with carrier mobility and velocity defined physically in terms of the Ge content x (0≤x≤0.50), and with threshold voltages (V_t) reduced due to the bandgap narrowing defined by x, but adjusted (for I_off control) to equal those of the Si-channel control devices, UFPDB/Spice3 simulations of 60 nm CMOS ring oscillators predict only a small speed enhancement when V_t is adjusted via channel doping. The peak enhancement is 5% for x=0.20. However, when a p⁺ poly-SiGe gate is used to adjust V_t of the pMOSFET, a peak 16% speed enhancement at x=0.30 is predicted; for pragmatic x=0.20, the enhancement is 14%.