Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process

The substrate-triggered technique for input, output, and power-rail electrostatic discharge (ESD) protection, as comparing to the traditional gate-driven technique, has been proposed to effectively improve ESD robustness of IC products. With the substrate-triggered technique, on-chip ESD protection circuits for the input, output, and power pins have been designed and verified in a 0.18-μm salicided CMOS process. The experimental results have confirmed that the proposed substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices. The human-body-model (HBM) ESD robustness of NMOS with a device dimension of W/L=300 μm/0.3 μm can be improved from the original 0.65 kV with the traditional gate-driven design to become 3.2 kV with the proposed substrate-triggered design.