Title :
Performance analysis of optimised CMOS comparator
Author :
Le, H.P. ; Zayegh, A. ; Singh, J.
Author_Institution :
Sch. of Electr. Eng., Victoria Univ., Melbourne, Vic., Australia
fDate :
5/29/2003 12:00:00 AM
Abstract :
A high-speed low-power latched CMOS comparator circuit is presented. Demonstrated is a circuit optimisation technique to obtain minimum offset error at 500 MHz sampling speed. Also, a mathematical model representing the noise in the device is developed. After optimisation, the comparator achieved 10-bit resolution on a 1 V differential input at 500 MHz speed and had a noise figure of 4.747 dB at this frequency.
Keywords :
CMOS analogue integrated circuits; circuit optimisation; comparators (circuits); integrated circuit noise; low-power electronics; 1 V; 4.747 dB; 500 MHz; circuit optimisation technique; comparator; differential input; low-power latched comparator circuit; mathematical model; minimum offset error; noise figure; optimised CMOS comparator; sampling speed;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20030546
