A data acquisition system for high rate chamber signals

Author

Skegg, Robert

Author_Institution

TRIUMF, Vancouver, BC, Canada

Volume

36

Issue

1

fYear

1989

fDate

2/1/1989 12:00:00 AM

Firstpage

826

Lastpage

827

Abstract

A CAMAC system which provides delays, data compaction and readout of signals from high-rate proportional wire chambers is presented. A delay buffer containing a large, fast shift register constructed from high-speed ECL RAMs (emitter-coupled-logic random-access memories) is described in detail. This provides up to 5 μs of delay with no deadtime for 32 binary data channels at a 20-ns sampling rate. A clock and gate distribution module synchronizes several delay modules for multichamber applications. A microprocessor is used to compact the data, thus reducing the volume before transmission to the main data acquisition system

Keywords

CAMAC; data acquisition; nuclear electronics; proportional counters; 20 ns; 5 mus; CAMAC; data acquisition system; data compaction; delay buffer; emitter-coupled-logic random-access memories; gate distribution module; high-rate proportional wire chambers; high-speed ECL RAMs; microprocessor; multichamber applications; readout; shift register; CAMAC; Clocks; Compaction; Data acquisition; Delay systems; Random access memory; Sampling methods; Shift registers; Synchronization; Wire;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.34559

Filename

34559