3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly

This paper presents a 3D interconnection scheme based on capacitive coupling. We propose synchronous communication circuits, based on a precharge and transmission approach, that provide an optimization of interconnection sensitivity. Measurements on a 0.13 ¿m CMOS implementation demonstrate working connections with an area occupation of 8 × 8 ¿m² . Experimental results are presented for both die-to-die and wafer-to-wafer assembly techniques. They show a maximum communication bandwidth of 1.23 Gb/s, leading to a throughput per area of 19 Mb/s/¿M² with an energy consumption of 0.14 mW/Gb/s. BER measurements demonstrate the reliability of these AC interconnections with no error on more than transmitted.