0.75-V four-quadrant current multiplier using floating gate-MOS transistors

Author

Kumngern, Montree ; Chanwutitum, Jirasak

Author_Institution

Dept. of Telecommun. Eng., King Mongkut´s Inst. of Technol. Ladkrabang, Bangkok, Thailand

fYear

2014

fDate

19-21 March 2014

Firstpage

1

Lastpage

4

Abstract

This paper presents a new ultra-low-voltage current-mode four-quadrant analog multiplier. A floating-gate technique is used to provide operating at a supply voltage of 0.75 V for the proposed circuit. PSPICE simulators using 0.18 μm TSMC CMOS process are used to show the workability of the multiplier. Simulation results show that the circuit has a linearity error of 1.5 % for the input current 8 μA, total harmonic distortion of 0.96 % for the input current 8 μA_peak and quiescent power consumption of 19.9 μW.

Keywords

CMOS analogue integrated circuits; MOSFET; circuit simulation; current-mode circuits; harmonic distortion; low-power electronics; voltage multipliers; PSPICE simulators; TSMC CMOS process; circuit simulation; current 8 muA; floating gate-MOS transistors; floating-gate technique; four-quadrant current multiplier; power 19.9 muW; power consumption; size 0.18 mum; total harmonic distortion; ultralow-voltage current-mode four-quadrant analog multiplier; voltage 0.75 V; Artificial neural networks; CMOS integrated circuits; CMOS technology; Linearity; analog multiplier; current-mode circuit; floating-gate MOS transistor; nonlinear circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering Congress (iEECON), 2014 International

Conference_Location

Chonburi

Type

conf

DOI

10.1109/iEECON.2014.6925870

Filename

6925870