A Comprehensive Study of Cobalt Salicide-Induced SRAM Leakage for 90-nm CMOS Technology

Cobalt salicide-induced static random access memory (SRAM) leakage in 90-nm technology is investigated in this paper. We found that the junction leakages are the origins of abnormal SRAM leakage, leading to a high direct-drain quiescent current and low function yield at wafer level. Cobalt salicide penetration at active edges is a dominant path for the junction leakage current. Both junction-area-intensive and active-edge-intensive test structures are employed to characterize the junction leakage. The SRAM function failure sites are carefully examined using conducting atomic force microscope and transmission electron microscope techniques. A full-factorial design of experiment (DOE) is implemented to systematically study the influences of Co thickness and temperatures of RTP1 and RTP2 on the junction leakage characteristics. Within the DOE window, it is found that both junction area and junction edge leakages increase with the Co thickness. The RTP1 temperature is critical in controlling Co salicide penetration at the active edge, while the RTP2 temperature is the main factor that affects the junction area leakage. SRAM leakage can be minimized by optimizing the salicide process scheme.