Title :
Low-power differential coefficients-based FIR filters using hardware-optimised multipliers
Author :
Vinod, A.P. ; Singla, A. ; Chang, C.H.
Author_Institution :
Sch. of Comput. Eng., Nanyang Technol. Univ.
fDate :
2/1/2007 12:00:00 AM
Abstract :
A minimal-difference differential coefficients method is presented for low power and high-speed realisation of differential-coefficients-based finite impulse response filters. The conventional differential coefficients method (DCM) uses the difference between adjacent coefficients whereas we identify the coefficients that have the least difference between their magnitude values and use these minimal difference values to encode the differential coefficients. Our minimal-difference differential coefficients can be coded using fewer bits, which in turn reduces the number of full additions required for coefficient multiplication. By employing a differential-coefficient partitioning algorithm and a pseudofloating-point representation, we show that the number of full adders and the net memory needed to implement the coefficient multipliers can be significantly reduced. The proposed method is combined with common subexpression elimination for further reduction of complexity. Experimental results show the average reductions of full adder, memory and energy dissipated achieved by our method over the DCM are 40, 35 and 50%, respectively
Keywords :
FIR filters; adders; floating point arithmetic; low-power electronics; multiplying circuits; FIR filters; differential-coefficient partitioning algorithm; differential-coefficients-based finite impulse response filters; full adders; hardware-optimised multipliers; high-speed realisation; low power realisation; minimal-difference differential coefficients; minimal-difference differential coefficients method; pseudofloating-point representation; subexpression elimination;
Journal_Title :
Circuits, Devices & Systems, IET
DOI :
10.1049/iet-cds:20050324