FPGA-based hardware/software implementation for MIMO wireless communications

This paper proposes an efficient architecture for FPGA implementation of MGS-QRD in MIMO wireless communication systems. The proposed architecture is based on the Hardware/Software (HW/SW) design. To achieve the efficient architecture, the systolic architecture is applied to MGS-QRD and then the conventional QR triangular array of (2m²+2m+1) cells onto a linear architecture of m+1 cell is employed to reduce the number of required QR processors. The reduced cells are constructed with a number of basic processing elements such as multipliers and adders etc. The basic elements are constructed by HW architectures. The SW of PowerPC core is used to control to achieve the QR decomposition. In this paper, utilization resource and operation performance in term of equivalent gates and operating cycles are shown.