DocumentCode :
122712
Title :
SAFER SLOTH: Efficient, hardware-tailored memory protection
Author :
Danner, Daniel ; Muller, Rudolf ; Schroder-Preikschat, Wolfgang ; Hofer, Wanja ; Lohmann, Daniel
Author_Institution :
Friedrich-Alexander-Univ. (FAU) Erlangen-Nurnberg, Erlangen, Germany
fYear :
2014
fDate :
15-17 April 2014
Firstpage :
37
Lastpage :
48
Abstract :
The goal of the SLOTH family of operating system kernels is to provide a unified priority space to the real-time applications. By automated mapping of tasks to interrupts, we eliminate rate-monotonic priority inversion and increase execution determinism. In its standard implementation, however, SLOTH has been criticized for being unsafe, since interrupt service routines are executed in supervisor mode. SAFER SLOTH mitigates this shortcoming-while keeping the favorable properties of SLOTH-and provides a safe and isolated execution environment for application tasks. Adopting the SLOTH philosophy of embracing and exploiting hardware particularities, its generative approach automatically tailors the system to both the application and the target architecture. We achieve efficient MPU-based memory protection at reduced latency and low performance overhead by leveraging code inlining and compiler optimizations. In comparison to a commercial AUTOSAR OS, SAFER SLOTH achieves speedups between 8x (worst case) and 23x (best case) on kernel latencies while retaining the SLOTH advantages of strict priority obedience, excellent determinism and small memory footprints.
Keywords :
interrupts; microprocessor chips; operating system kernels; optimising compilers; storage management; AUTOSAR OS; MPU-based memory protection; SAFER SLOTH; SLOTH operating system kernel family; automated tasks mapping; code inlining; compiler optimizations; execution determinism; hardware-tailored memory protection; interrupt service routines; interrupts; rate-monotonic priority inversion; small memory footprints; strict priority obedience; supervisor mode; Automotive engineering; Hardware; Kernel; Memory management; Registers; Safety; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 IEEE 20th
Conference_Location :
Berlin
ISSN :
1080-1812
Print_ISBN :
978-1-4799-4691-4
Type :
conf
DOI :
10.1109/RTAS.2014.6925989
Filename :
6925989
Link To Document :
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