Implementation of error correcting methods for asynchronous communication and modified completion detector with reduced area overhead

This paper describes the design for correcting errors in asynchronous global communication. These are unordered delay insensitive (DI) codes and uses four-phase return-to-zero protocol, as it provides simple and fast implementation and they are widely used. This paper provides 1-bit and also 2-bit error correcting methods. Two bit error correction coverage is up to 55%-70%, providing better or comparable coding efficiency. Designs given build on prior work of [1] and this paper proposes a small modification to their work. Practical implementation for 1-bit and 2-bit error correcting method is also provided by using Xilinx tools. Parity generator and checker are used for multiple error detection. This paper provides a novel completion detector with reduced area overhead. These codes were simulated using modelsim tool version 10.2b and implemented in Xilinx spatran3 FPGA.