DocumentCode :
122757
Title :
VLSI (FPGA) design for distinctive division architecture using the Vedic sutra ‘Dhwajam’
Author :
Oke, Shantanu ; Lulla, Suraj ; Lad, Prathamesh
Author_Institution :
Maharashtra Inst. of Technol., Pune, India
fYear :
2014
fDate :
6-8 March 2014
Firstpage :
1
Lastpage :
4
Abstract :
In this paper we have discussed the VLSI implementation of a unique division architecture using a method known as the `Dhwajam´, a novel method, from the annals of Vedic Mathematics. Vedic Mathematics is an antediluvian branch of Indian mathematics with sixteen special formulae. The `Dhwajam´, also known as the flag method, shows exceptionally low computational complexity as described. The `Dhwajam´ is unique in a way that it can be generalized, be exploited to the fullest with large scale implementation and has not been explored before. Its inherent parallelism too is much suitable for VLSI implementation. The division scheme was implemented in Xilinx 8.1 ISE and results were tested on spartan3 FPGA platform.
Keywords :
VLSI; circuit complexity; field programmable gate arrays; logic design; Indian mathematics; VLSI implementation; Vedic Mathematics; Vedic Sutra Dhwajam; Xilinx 8.1 ISE; distinctive division architecture; flag method; low computational complexity; spartan3 FPGA platform; Adders; Computational complexity; Computer architecture; Delays; Field programmable gate arrays; Very large scale integration; Division without division; Modified ‘Dhwajam’; Operational and Computational complexity; Spartan3 FPGA; VHDL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Devices, Circuits and Systems (ICDCS), 2014 2nd International Conference on
Conference_Location :
Combiatore
Type :
conf
DOI :
10.1109/ICDCSyst.2014.6926137
Filename :
6926137
Link To Document :
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